Switchbox routing in VLSI design: Closing the complexity gap

Closing the SoC Design Gap

E mbedded systems are ubiquitous , and they represent the major market for microprocessors. In fact, more than one billion microprocessors find their way into embedded systems every year, and this number will continue to grow rapidly. One reason for this phenomenon is that intense competition among man-ufacturers—especially for mainstream consumer products—has shortened the life cycles for prod...

Design Rules in VLSI Routing

Closing a Gap in the Complexity of Refinement Modal Logic

Refinement Modal Logic (RML), which was recently introduced by Bozzelli et al., is an extension of classical modal logic which allows one to reason about a changing model. In this paper we study computational complexity questions related to this logic, settling a number of open problems. Specifically, we study the complexity of satisfiability for the existential fragment of RML, a problem posed...

Switchbox routing by stepwise reshaping

An algorithm for switchbox routing, called PACKER, is presented. In an initial phase, the connectivity of each net is established in a fast way without taking the other nets into account. In general this will give rise to conflicts (short circuits). In the second stage the conflicts are removed iteratively using Connectivity preserving local transformations (CPLT’s). They “reshape” a net by dis...

Routing Through a Generalized Switchbox

We present an algorithm for the routing problem for two-tenninal nets in generalized switchboxes. A generalized s\~itchbox is any subset R of the planar rectangular grid with no non-trivial holes, i.e. every finite face has exactly four incident vertices. A net is a pair of nodes of non-maximal degree on the boundary of R. A solution is a set of edge-disjoint paths, one for each net. Our algori...